Power and system management information visibility

ABSTRACT

Aspects of power and system management information visibility are described. In various embodiments, a system parameter of a system is measured. The system parameter may include one or more parameters such as system voltages, temperatures, options, or conditions of the system. The system parameter may be evaluated by a power manager processor. The evaluation may determine operating settings for one or more elements of the system. Based on the evaluation, one or more operating parameters for elements of the system may be set, in advance of powering up the system elements. After the operating parameters have been set, system elements may be released to start or boot based on the operating parameters. In this manner, one or more elements of the system may power on in a more flexible and deliberate manner, taking the current operating environment of the system into consideration.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims the benefit of:

U.S. Provisional Application No. 61/759,470, filed Feb. 1, 2013;

U.S. Provisional Application No. 61/833,598, filed Jun. 11, 2013;

U.S. Provisional Application No. 61/834,513, filed Jun. 13, 2013;

U.S. Provisional Application No. 61/836,327, filed Jun. 18, 2013;

U.S. Provisional Application No. 61/836,306, filed Jun. 18, 2013;

U.S. Provisional Application No. 61/836,895, filed Jun. 19, 2013;

U.S. Provisional Application No. 61/836,886, filed Jun. 19, 2013; and

U.S. Provisional Application No. 61/836,903, filed Jun. 19, 2013, the entire contents of each of which are hereby incorporated herein by reference.

This application also makes reference to:

U.S. patent application Ser. No. ______ (Attorney Docket #50229-4880), titled “Clock Domain Crossing Serial Interface, Direct Latching, and Response Codes” and filed on even date herewith;

U.S. patent application Ser. No. ______ (Attorney Docket #50229-4900), titled “Power Mode Register Reduction and Power Rail Bring Up Enhancement” and filed on even date herewith;

U.S. patent application Ser. No. ______ (Attorney Docket #50229-4910), titled “Dynamic Power Profiling” and filed on even date herewith;

U.S. patent application Ser. No. ______ (Attorney Docket #50229-4920), titled “Charger Detection and Optimization Prior to Host Control” and filed on even date herewith;

U.S. patent application Ser. No. ______ (Attorney Docket #50229-4940), titled “Enhanced Recovery Mechanism” and filed on even date herewith; and

U.S. patent application Ser. No. ______ (Attorney Docket #50229-4960), titled “Dynamic Power Mode Switching Per Rail” and filed on even date herewith, the entire contents of each of which are hereby incorporated herein by reference.

BACKGROUND

Battery-powered computing systems and devices have been adopted for use in many aspects of daily life. As these systems and devices are more widely adopted and used in place of other computing systems and devices, they are designed to be more flexible and powerful, but are also more complex. With advances in the design of battery-powered computing devices, the availability of sufficient power for the devices continues to be an ongoing concern. For example, each new feature in a battery-powered computing device may require the provision of circuitry that supports a supply of power for the feature.

In the context of system power management, some battery-powered computing systems include power management processing circuitry that manages the supply of power in the system. Over time, this power management processing circuitry may need to evolve to better adapt to battery-related concerns such as flexibility and control in battery discharging, flexibility and control in battery charging, and flexibility and control in battery charge management and conservation.

BRIEF DESCRIPTION OF THE DRAWINGS

Many aspects of the present disclosure can be better understood with reference to the following drawings. The components in the drawings are not necessarily to scale, with emphasis instead being placed upon clearly illustrating the principles of the disclosure. Moreover, in the drawings, like reference numerals designate corresponding parts throughout the several views.

FIG. 1 illustrates a system for power system management information visibility according to an example embodiment.

FIG. 2A illustrates a process flow diagram for a method of power and system management information visibility performed by the system of FIG. 1 according to an example embodiment.

FIG. 2B illustrates the process flow diagram for the method of power and system management information visibility performed by the system of FIG. 1 according to an example embodiment.

FIG. 3 illustrates a process flow diagram for a method of evaluation of power and system management information performed by the system of FIG. 1 according to an example embodiment.

DETAILED DESCRIPTION

In the context of system power management, some battery-powered computing systems include power management processing circuitry that manages the supply of power in the system. Over time, this power management processing circuitry may need to evolve to better adapt to battery-related concerns such as flexibility and control in battery discharging, flexibility and control in battery charging, and flexibility and control in battery charge management and conservation.

Additionally, the need for power management processing circuitry to balance problems related to battery charging and discharging in the context of a user's experience is now more important. Engineers now consider a full array of problems associated with battery charging and discharging in the context of user experience. For example, even when a battery is substantially discharged, a user desires battery-powered computing systems and devices to power up promptly when coupled to power for charging, regardless of the fact that a minimum threshold of charge and/or voltage may be necessary in the battery. Similarly, engineers must consider certain aims of manufacturing and testing that achieve high volume production of battery-powered computing systems and devices.

In this context, aspects of power and system management information visibility are described herein. In various embodiments, a system parameter of a system is measured. The system parameter may include one or more parameters such as system voltages, temperatures, options, or conditions of the system. The system parameter may be evaluated by a power manager processor. The evaluation may determine operating settings for one or more elements of the system. Based on the evaluation, one or more operating parameters for elements of the system may be set, in advance of powering up the system elements. After the operating parameters have been set, system elements may be released to start or boot based on the operating parameters. In this manner, one or more elements of the system may power on in a more flexible and deliberate manner, taking the current operating environment of the system into consideration.

Turning now to the drawings, an introduction and general description of exemplary embodiments of a system is provided, followed by a description of the operation of the same.

I. System Introduction

FIG. 1 illustrates a system 10 for power system management information visibility according to an example embodiment. The system 10 may embody a computing device that includes a number of general and/or specific purpose circuits, processing circuits, processors, registers, memories, sensors, displays, etc. In one embodiment, the system 10 may embody a handheld or portable computing device which is powered from charge stored in a battery. In various embodiments, the system 10 may be embodied as part of a cellular telephone, tablet computing device, laptop computer, or other computing device. Alternatively, because the embodiments described herein are not limited to use in handheld or portable computing devices, the system 10 may be embodied as part of a desktop or set top computing device, for example. Although not illustrated in FIG. 1, it should be appreciated that the system 10 may include one or more displays, microphones, speakers, buttons, indicator lights, haptic feedback elements, memory card readers, etc.

Among other elements, the system 10 includes a power management unit (PMU) 100, a host system-on-chip (SOC) 130, a system bus 180, a system battery 182, and a system memory 184. The system 10 also includes certain subsystems such as a bluetooth/wireless local area network (WLAN) subsystem 170, a global positioning system (GPS) subsystem 171, a camera subsystem 172, and a sensor subsystem 173. The subsystems 170-173 are representative subsystems which may be included as elements of the system 10, and other subsystems are within the scope and spirit of the embodiments described herein. It is noted that, just as the host SOC 130 requires power for operation, each of the subsystems 170-173, the system memory 184, and other elements and circuits of the system 10 depend on power for operation. As discussed below, this power may be supplied by and under the control of the PMU 100.

The system bus 180 of the system 10 is electrically and communicatively coupled among the PMU 100 and the host SOC 130. As discussed herein, the system bus 180 may be relied upon by the system 10 for both data communications to external computing systems and peripherals, and to electrically couple a supply of power to the system 10 for charging the system battery 182. The system bus 180 may include any communications bus suitable for the application, such as the universal serial bus (USB), although the use of other serial and/or parallel bus topologies are within the scope and spirit of the embodiments described herein.

The system battery 182 may be embodied as any rechargeable battery suitable for the application, such as a lithium-ion, nickel-metal-hydride, or other battery variant, without limitation. The system memory 184 may be embodied as a volatile and/or non-volatile random access memory or combination thereof. The system memory 184 may store computer-readable instructions thereon that, when executed by one or more of the processors 140-142 of the host SOC 130, for example, direct the processors 140-142 to execute various aspects of the embodiments described herein.

In general, the PMU 100 controls and/or facilitates control of the distribution of power from the system battery 182 to the elements of the system 10, such as the host SOC 130, the subsystems 170-173, and the system memory 184, for example. As further described below, depending upon the operating state of the system 10 and/or other factors, the PMU 100 may control the distribution of power to one or more elements of the system 10, and the PMU 100 may receive instructions to control the distribution of power to one or more elements of the system 10.

Among other elements, the PMU 100 includes a PMU controller 101, a serial interface slave 102, a PMU register bank 103, a charger detect/protect circuit 104, a battery charger circuit 105, a one time programmable (OTP) map 106, a current (/) sense circuit 107, a number 0-N of analog-to-digital (ADC) circuits 110-112, and a number of power rail circuits 120-124. It is noted that FIG. 1 illustrates a representative example of elements of the PMU 100, and it should be appreciated that the PMU 100 may include other elements in various embodiments. That is, the PMU 100 may include a number of power rail circuits in addition to the power rail circuits 120-124. For example, the PMU 100 may include an additional power rail circuit to provide power for the system memory 184, among other additional power rails.

Among other elements, the host SOC 130 includes general and/or application specific processors. In FIG. 1, the host SOC 130 includes a power manager 131, an application processor 140, a modem 141, and a graphics processor 142. In various embodiments, the host SOC 130 may omit one or more of the processors 140-142 or include processors in addition to the processors 140-142. The host SOC 130 also includes a system bus interface 160, a battery charger detect (BCD) circuit 161, a subsystem interface 162, and memory interface 163. The subsystem interface 162, the memory interface 163, and the system bus interface 160 electrically and communicatively couple the subsystems 170-173, the system memory 184, and the system bus 180 to the host SOC 130 and, particularly, to one or more of the processors 140-142.

As further illustrated in FIG. 1, each of the application processor 140, the modem 141, and the graphics processor 142 includes a respective register bank 150, 151, and 152. In other embodiments, the register banks 150, 151, and 152 may be combined and shared among the processors 140-142. Still other configurations and/or combinations of the register banks 150, 151, and 152 are within the scope and spirit of the embodiments described herein. These register banks may be relied upon by the power manager 131, generally, to set operating parameters for the application processor 140, the modem 141, and the graphics processor 142, as further described below.

The application processor 140 may be embodied as a general purpose processor for executing various applications. For example, the application processor 140 may execute an underlying operating system along with applications such as e-mail, short message service (SMS), telephone, camera, web-browser, and other applications, without limitation. As compared to the PMU 100 and/or the power manager 131, the application processor 140 may consume relatively more power during operation. The modem 141 may include a cellular-based (or similar) communications processor for the communication of data wirelessly in connection with radio-frequency front end circuitry, and the graphics processor 142 may include a processor for driving a display of the system 10.

The power manager 131 includes a power processor 132, a memory 133, and a serial interface master 134. Generally, the power manager 131 may be embodied as a relatively small and low power processor or processing circuit for interfacing with the PMU 100 via a serial interface 128. In one embodiment, the serial interface master 134 of the power manager 131 controls the serial interface 128, although the PMU 100 may control the serial interface 128 in other embodiments. The memory 133 stores computer-readable instructions for execution by the power processor 132.

It is noted that, in certain embodiments, the host SOC 130 (including the power manager 131) and the PMU 100 may be combined in an integrated circuit. In this case, the serial interface 128 may be omitted.

II. System Operation

With reference to the elements of the system 10 introduced above, aspects of the operation of the system 10 are described below.

A. PMU Operation

The PMU 100 may be designed, adapted, and configured to perform operations that support the host SOC 130, the subsystems 170-173, the system memory 184, and other elements of the system 10. For example, the PMU 100 may remain in a powered-on mode of operation, even when the host SOC 130 and other elements of the system 10 are in a powered-off mode of operation. The PMU 100 may be maintained in the powered-on mode of operation so as to gather system parameters for the system 10, such as power and management system status data (i.e., “system parameters,” “system status data”, etc.), regardless of whether the host SOC 130 and other elements of the system 10 are off.

It is noted that a certain amount of overhead processing is relied upon in the system 10, such as battery charging, maintenance of a real time clock, etc., and this overhead processing may be generally performed by the PMU 100 regardless of whether the host SOC 130 and other elements of the system 10 are powered off. In this context, while the system 10 remains in a powered-off mode of operation (except for the PMU 100 in most cases), the PMU 100 is designed to consume a relatively small amount of power from the system battery 182 because power may be limited and the system battery 182 may be discharging.

The PMU controller 101 generally coordinates and controls the operations of the PMU 100. The PMU controller 101 may be embodied as a general or specific purpose circuit, processing circuit, processor, state machine, etc. The PMU controller 101 interfaces with the charger detect/protect circuit 104 and the battery charger circuit 105 to charge the system battery 182 when power for charging is available, interfaces with the serial interface slave 102 to communicate with the host SOC 130 over the serial interface 128, interfaces with the power rail circuits 120-124 to control power to the system 10, and interfaces with the PMU register bank 103 to store and access data associated with the status of the PMU 100 and the system 10. Additionally, the PMU controller 101 interfaces with other elements of the PMU 100, such as the ADCs 110-112, the current sense circuit 107, and the OTP map 106.

The serial interface slave 102 comprises one end of the serial interface 128 that facilitates communication between the PMU 100 and the host SOC 130. Among various modes and states of operation of the system 10, the serial interface 128 is relied upon to communicate system parameters or system status data between the PMU 100 and the host SOC 130. For example, the PMU 100 may gather data regarding a type of battery charger or charging port coupled to the system bus 180, a battery voltage of the system battery 182 (i.e., VBat), a bus voltage on the system bus 180 (i.e., VBus), a temperature of a component of the system 10, whether a feature option in the system 10 is set, and/or whether the system bus 180 is coupled to a system or device that hosts a program image source which may be retrieved by the system 10. In part, this system status data may be gathered using one or more of the ADCs 110-112. For example, the ADCs 110-112 may be relied upon to determine the VBat and VBus voltages, the temperature of components in the system 10, etc. Particularly, the ADCs 110-112 may convert analog values of the VBat and VBus voltages, and voltages representative of the temperature of components in the system 10, into digital values for processing and/or storage by the PMU 100. While these and other examples of power and management system parameters and system status data are described herein, other types of data representative of the status of the system 10 are within the scope and spirit of the embodiments.

In general, the system parameters, system status data, etc. may be representative of operational aspects of the system 10 and may be gathered by the PMU 100 from time to time, periodically or aperiodically over time, as directed by the host SOC 130, or at any other suitable time(s). The system status data may be stored by the PMU controller 101 in the PMU register bank 103 and, in certain embodiments described herein, communicated to the host SOC 130 for further evaluation and processing.

In connection with the BCD circuit 161 of the host SOC 130, the charger detect/protect circuit 104 may be relied upon to detect the type of battery charger or charging port coupled to the system bus 180 and report the type of battery charger or charging port to the PMU controller 101. The charger detect/protect circuit 104 may determine an amount of power that a charger or port coupled to the system bus 180 is able to supply. For example, depending upon the type of charger or port coupled to the system bus 180, the charger or port may be able to source a current of between 100 mA and 1.5 A or more at a certain voltage, without collapse.

The charger detect/protect circuit 104 may also be able to distinguish whether the system bus 180 is coupled to a charging downstream port (CDP), a dedicated charging port (DCP), an accessory charging adapter port (ACA), a personal system 2 (PS/2) port, or a standard downstream port (SDP). Each of these ports may be able to source a certain amount of power to the system 10. In certain aspects of the embodiments described herein, the system 10 may be able to tailor its operation based on the amount of power available to charge the system battery 182, for example.

When the system 10 is coupled to charging power via the system bus 180, the battery charger circuit 105 may charge the system battery 182 based on or in accordance with the type of battery charger or port coupled to the bus 180. For example, depending upon the amount of power available to charge the system battery 182, which may depend in part based on the type of battery charger or port coupled to the bus 180, the battery charger circuit 105 may charge the system battery 182 relatively slowly or quickly. In addition to the VBat and VBus voltages, a charging status of the system battery 182 may be stored by the PMU controller 101 in the PMU register bank 103.

The OTP map 106 includes an array of programmable fuses or similar circuit elements that may each be programmed to retain a logical value. In this context, the OTP map 106 may be programmed during an initial test of the PMU 100 after manufacture, for example, or at another suitable time. The logical values retained in the OTP map 106 may be referenced by the PMU controller 101, to direct conditional operation of the PMU controller 101. For example, the logical values retained in the OTP map 106 may be relied upon to store initial voltage settings, for example, for one or more of the power rail circuits 120-124. That is, the OTP map 106 may store voltage and/or current settings for power supplied by one or more of the system bus interface power rail 120, the BCD power rail 121, the power processor power rail 122, the I/O pin power rail 123, and/or the application processor (AP) power rail 124. Depending upon the operating status of the system 10, the PMU controller 101 may directly set the voltage and/or current settings for one or more of the power rails 120-124 based on the logical values retained in the OTP map 106, for example, and/or other factors. Additionally or alternatively, depending upon the operating status of the system 10, the PMU controller 101 may set voltage and/or current settings for one or more of the power rails 120-124 based on instructions from the host SOC 130, as further described below.

In other aspects, the OTP map 106 may store settings associated with different battery chargers or charging ports which may be coupled to the system bus 180. As noted above, depending upon the type of charger or port coupled to the system bus 180, a current of between 100 mA and 1.5 A or more may be available for charging the system battery 182 and other functions of the system 10. In this context, the OTP map 106 may store certain settings for battery charging, rail voltages, power-up sequences, system limitations, etc., depending upon the type of charger or port coupled to the system bus 180. Further, the OTP map may store settings associated with other system parameters measured and/or evaluated by the PMU 100.

The current sense circuit 107 may be relied upon by the PMU 100 to determine the current being supplied by each of the power rails 120-124. Particularly, using representative-scale replica power rail circuits, the current sense circuit 107 may sense and determine instant or average current being supplied by each of the power rails 120-124 from time to time or over a period of time as directed by the PMU controller 101. Further, the current sense circuit 107 may sample and convert analog representations of the current being supplied by each of the power rails 120-124 into digital values. These values may be stored by the PMU controller 101 in the PMU register bank 103 as system status data.

In certain modes and states of operation of the system 10, the PMU 100 may rely upon a strap switch 129 to electrically couple power from the system bus 180 (i.e., VBus) to one or more of the power rails 120-124 (or other power rails), and to electrically de-couple power from the system battery 182 (i.e., VBat) from the one or more of the power rails 120-124. In this context, the strap switch 129 may couple power from the system bus 180 to one or more of the power rails 120-124 if the system battery 182 lacks sufficient voltage for the operation of certain elements in the system 10 within operating requirements. In various embodiments, it is noted that the strap switch 129 may include one or more switches, as well as protection and/or regulation circuitry that filters and/or conditions power coupled to the system 10 via the system bus 180.

As one example use of the strap switch 129, the PMU controller 101 may control the strap switch 129 to couple power from the system bus 180 to a power rail for the system memory 184, for at least a limited period of time, if the system battery 182 has not yet reached a threshold voltage (e.g., ˜3.2 V) required for stable operation of the system memory 184. It is noted that, among the elements in the system 10, certain elements may require a relatively higher voltage for operation than others. Rather than waiting for the system battery 182 to charge to the relatively higher voltage necessary for these elements, the strap switch 129 may be relied upon to provide the VBus voltage, rather than the VBat voltage, to the power rails for these elements. In turn, the power rails may regulate and/or condition the VBus voltage from the system bus 180 to a voltage suitable for operation of the elements that require the relatively higher voltage. In this way, the system 10 may be started faster, because it is not necessary to wait for the system battery 182 to charge to the relatively higher voltage. Elements in the system 10 that do not require the relatively higher voltage may be powered by power rails supplied by the voltage VBat from the system battery 182. After the voltage VBat of the system battery 182 reaches a voltage sufficient to support the relatively higher voltage, the strap switch 129 may again couple power from the system battery 182 to the power rails for the elements which require the relatively higher voltage.

B. Host SOC Operation

The host SOC 130 may be generally embodied as a full system-on-chip semiconductor device. In this sense, the host SOC 130 integrates various general and/or application specific processors and processing circuits into a single integrated circuit package, reducing space. Overall, the power manager 131 of the host SOC 130 supports the host SOC 130 and the power requirements of the host SOC 130.

The power manager 131 of the host SOC 130 may retrieve and evaluate the power and management system status data stored in the PMU 100, while coordinating a power up sequence for the host SOC 130 and/or the subsystems 170-173 with the PMU 100. As described in further detail below, the power processor 132 of the power manager 131 and the PMU 100 may operate in connection with each other to power up elements in the system 10 based on the power and management system status data gathered by the PMU 100. On the basis of the system status data, the power manager 131 and the PMU 100 may conditionally power up elements in the system 10 in various sequences or modes of operation.

In the context of power up of the host SOC 130, it is noted that each of the power manager 131, the application processor 140, the modem 141, and the graphics processor 142 may be powered by one or more power rails of the PMU 100 in the system 10. For example, in the embodiment illustrated in FIG. 1, the power manager 131 is powered by the power processor power rail 122, and the application processor 140 is powered by the application processor power rail 124. In various embodiments, it is noted that several elements of the system 10 may be powered by one of the power rails of the PMU 100, although individual ones of those elements may be respectively switched between powered-off and powered-on modes of operation by control signals, for example. Each power rail may be electrically coupled from the PMU 100 to the host SOC 130 by one or more respective power traces in the system 10 and power pins or pads of the PMU 100 and the host SOC 130. Other power rails of the PMU 100 are respectively coupled to system elements in the system 10, as necessary, for supplying power.

According to certain aspects described herein, because the power manager 131 of the host SOC 130 operates as a type of partner with the PMU 100 for power management in the system 10, the PMU 100 generally powers and releases the power manager 131 for start while the remaining processors and systems of the host SOC 130 and/or the system 10 are left without power until a later time.

In view of the context provided above, it is noted that each of the application processor 140, the modem 141, the graphics processor 142, and other system elements may be transitioned from a powered-off to a powered-on mode of operation at a different respective time or timing, as determined by the PMU 100 and/or the power manager 131. Further, these elements may be powered-on according to a certain mode of operation for optimal power consumption. According to aspects of the embodiments described herein, in the interest of overall flexibility in power-up of the system 10, especially in cases of low power in the system battery 182, high or abnormal system temperature, connection of the system bus 180 to a system or device that hosts an image for download, etc., the PMU 100 and the power manager 131 may evaluate the power and management system status data which is gathered and stored by the PMU 100, to determine an appropriate manner in which the elements, subsystems, and processors of the system 10 are powered on.

As one example of a conditional power up, the power manager 131 may retrieve and evaluate a system parameter stored by the PMU 100, evaluate the system parameter, and set an operating parameter for the application processor 140 based on the evaluation of the system parameter. The operating parameter may be set (e.g., stored) by the power manager 131 in the register bank 150 of the host SOC 130 for reference by the application processor 140 and/or other supporting circuitry during a boot up sequence of the application processor 140. After the PMU 100 powers the application processor power rail 124 (and any other necessary power rails), the application processor 140 may be released for start (e.g., boot).

The boot sequence of the application processor 140 may be impacted by the operating parameter which was set or stored in the register bank 150 by the power manager 131 before the application processor 140 was released for start. As one example, the operating parameter may indicate that the application processor 140 must boot at a certain operating frequency or speed for lower power operation because the battery voltage VBat of the system battery 182 is marginal. That is, the charge stored in the system battery 182 may be sufficient only to support a low frequency—rather than a high frequency—boot of the application processor 140. Alternatively, the operating parameter may indicate that the application processor 140 must boot according to a certain limitation of operating power or timing, to conserve power. Here, it should be appreciated that the application processor 140 may consume relatively more power than the PMU 100 and/or the power manager 131, even in combination with each other, unless the operating parameters of the application processor 140 are configured for low power operation.

In the context of a conditional power up, generally, the conditions for power up may be determined such that the current consumed by the system 10 during boot is less than the charging current provided to the system battery 182 for charging. Particularly, after the BCD detect circuit 161 detects the type of battery charger or charging port coupled to the system bus 180, and the OTP map is referenced to ascertain the maximum charging current available for the charger or charging port, the system 10 may be configured according to aspects of the embodiments described herein to consume relatively less power during boot than is currently being used to charge the system battery 182. In this way, the system 10 may be booted, even if with certain limitations or conditions on power consumption, safely and quickly, although the system battery 182 may be substantially discharged.

Especially if the system battery 182 is fully discharged, the time period from coupling the system 10 to a power source until conditional power up of the system 10 may be significantly less than would otherwise be needed, because the system 10 is configured to power up with a certain, limited, current consumption. Even after a conditional power up, however, the system 10 continues to monitor system parameters including the voltage VBus of the system battery 182, and operating parameters of the system 10 may be adjusted over time as further described below.

In other aspects, a conditional power up and continued low-power operation may be relied upon to charge a battery faster than would otherwise be possible. In other words, with a certain current available for charging the system battery 182, the system 10 may be powered up and operated in accordance with settings for lower power consumption, and any savings in consumed power may be directed to charging the system battery 182 more quickly. Additional examples of the evaluation of system parameters and conditional and/or directed boot modes, sequences, mode of operation, etc. in the system 10 are described in further detail below with reference to FIGS. 2A, 2B, and 3.

Turning to FIGS. 2A, 2B, and 3, process flow diagrams illustrating example processes performed by a system for power and system management information visibility. While the process flow diagrams are described in connection with the system 10 of FIG. 1, it is noted that other systems may perform the illustrated processes. That is, in various embodiments, systems similar to the system 10 may perform the processes illustrated in FIGS. 2A, 2B, and 3.

In certain aspects, the flowcharts of FIGS. 2A, 2B, and 3 may be considered to depict example steps performed by the system 10 according to one or more embodiments. Although the process diagrams of FIGS. 2A, 2B, and 3 illustrate an order, it is understood that the order may differ from that which is depicted. For example, an order of two or more elements in the process may be scrambled relative to that shown, performed concurrently, or performed with partial concurrence. Further, in some embodiments, one or more of the elements may be skipped or omitted within the scope and spirit of the embodiments described herein.

FIG. 2A illustrates a process flow diagram for a method 200 of power and system management information visibility performed by the system 10 of FIG. 1 according to an example embodiment. It may be assumed that the system 10 is in a powered-off mode of operation at the outset of the method 200. However, even when the host SOC 130 and other elements of the system 10 are in the powered-off mode of operation, the PMU 100 of the system 10 may be maintained in a powered-on mode of operation so as to gather system parameters for the system 10.

At reference numeral 202, the method 200 includes measuring a system parameter. That is, in the context of the system 10 of FIG. 1, the PMU 100 may measure, identify, and/or determine one or more system parameters of the system 10 at reference numeral 202. The system parameters may include one or more voltages, one or more currents, one or more temperatures, one or more feature options, or other system parameters. In general, at reference numeral 202, the PMU 100 may measure, identify, and/or determine any of the system parameters described herein or similar system parameters.

As one example, as discussed above, the ADCs 110-112 of the PMU 100 may convert the VBat and VBus voltages and voltages representative of the temperature of elements in the system 10 into digital values for measurement and storage. Additionally, the PMU 100 may identify a type of battery charger or charging port coupled to the system bus 180. The PMU 100 may also refer to the OTP map 106 to identify initial voltage settings for the power rail circuits 120-124 and an initial charging current supplied by the battery charger circuit 105 to the system battery 182 based on the type of battery charger or charging port coupled to the system bus 180. These initial voltage settings may be identified by the PMU 100 as system parameters.

As another example, the PMU 100 may identify one or more feature options. A feature option of the PMU 100 may be identified based on a voltage strapped to a pin or pad of the PMU 100. In other words, a relatively high-impedance resistor may be used to electrically couple a logic-high voltage level to a pin or pad of the PMU 100. This logic-high voltage level may be identified by the PMU 100 at reference numeral 202. The logic-high voltage level may indicate to the PMU 100 that, for example, an external battery charger detection circuit is being relied upon in the system 10, that an external wireless charging circuit is being relied upon in the system 10, or that the system 10 is currently under test, etc. These feature option settings may be identified by the PMU 100 as system parameters.

At reference numeral 204, the method 200 includes storing the system parameters that were measured, identified, and/or determined at reference numeral 202. As described above, the PMU 100 may store the system parameters into the PMU register bank 103. It should be appreciated that, in various embodiments, the measuring at reference numeral 202 and the storing at reference numeral 204 may continue to be performed throughout the process flow of the method 200 and other processes of the system 10. In other words, the PMU 100 may continue to measure, store, and evaluate system parameters of the system 10 over time, and those functions of the PMU 100 should not be considered to be limited to any period of time in the process flow of the method 200 or other processes of the system 10.

At reference numeral 206, the method 200 includes determining whether to start the power manager 131 of the host SOC 130. For example, at reference numeral 206, the PMU 100 may determine whether to start the power manager 131, based on certain factors and considerations. For example, the determination of whether to start the power manager 131 may depend upon whether a minimum threshold of charge and/or voltage is available in the system battery 182 to supply power to the power rails (e.g., power rails 122, 123, etc.) that support the power manager 131. Alternatively or additionally, the determination of whether to start the power manager 131 may depend upon a certain timing, whether a power button of the system 10 was pressed, whether a certain battery charger or port type is coupled to the system bus 180, or combinations of these considerations, among others.

If the PMU 100 determines at reference numeral 206 not to start the power manager 131, then the method 200 proceeds back to reference numeral 202 to continue to measure system parameters of the system 10. On the other hand, if the PMU 100 determines at reference numeral 206 to release the power manager 131, then the method 200 proceeds to reference numeral 208.

At reference numeral 208, the method 200 includes powering one or more power rails for the power manager 131. Thus, at reference numeral 208, the PMU 100 may refer to the OTP map 106 to identify initial voltage settings for one or more of the power rail circuits 120-124, and set the one or more power rail circuits 120-124 to an output voltage according to the initial voltage settings. In various embodiments, the one or more power rails may include only those necessary to supply power to the power processor 132, the memory 133, the serial interface master 134, and certain I/O pins.

At reference numeral 210, the method 200 includes updating the system parameters. Here, the PMU 100 may update or revise system parameters stored in the PMU register bank 103 on the basis of any system status parameters that have recently changed. In this context, it is noted that the PMU 100 may update or revise the system parameters stored in the PMU register bank 103 at any time and over time throughout the process flow of the method 200 and other processes of the system 10. In this manner, the most up-to-date system status parameters are available for retrieval and evaluation.

At reference numeral 212, the method 200 includes releasing the power manager 131 to start. Here, for example, the PMU 100 may release the power manager 131 to start by changing a logic level on a reset pin of the host SOC 130 for the power manager 131. Upon the release, the power manager 131 boots and seeks status information on the system 10 from the PMU 100. Relying upon the serial interface master 134, the power processor 132 may request communication of (or send a command for) system parameters from the PMU 100 via the serial interface 128. Based on the request or command from the power processor 132, at reference numeral 213, the method 200 includes the PMU 100 communicating one or more system parameters to the power processor 132 via the serial interface 128. Particularly, the PMU controller 101 accesses the PMU register bank 103 to retrieve one or more system parameters and then communicates the system parameters back to the power processor 132 via the serial interface 128.

Turning to FIG. 2B, at reference numeral 214, the method 200 includes evaluating one or more system parameters. Particularly, the power processor 132 evaluates the system parameters received from the PMU 100 for various purposes, including to determine the operating conditions and environment of the system 10. In certain aspects, the evaluating at reference 214 is performed to determine whether the application processor 140 of the host SOC is ready to power on, or to assist one or more elements of the system 10 to power on in a flexible and deliberate manner, taking into consideration the current operating environment of the system 10. Further details on the evaluating are described below with reference to FIG. 3.

At reference numeral 216, the method 200 includes setting one or more operating parameters for one or more of the application processor 140, the modem 141, the graphics processor 142, one or more of the subsystems 170-173, or other elements of the system 10, for example, based on the evaluation at reference numeral 214. It is noted that, at reference numeral 216, one or more operating parameters may be set for a combination of features of the application processor 140, the modem 141, and the graphics processor 142, and other elements of the system 10 based on the evaluation at reference numeral 214.

Setting the operating parameters may be performed by the power processor 132 by storing data, flags, or logic levels, for example, in the register banks 150-152. For example, if the evaluating at reference numeral 214 identifies that the voltage level VBat is marginal, an operating parameter for the application processor 140 may be set by the power processor 132 in the register bank 150. This operating parameter may identify that, when the application processor 140 is released to start or boot, it must boot at a relatively lower operating frequency than would otherwise be permitted if the voltage level VBat was higher. As another example, the application processor 140 may be released to start with a condition or limit on the brightness that may be set for a display of the system 10. According to certain aspects, operating parameters may be set at reference numeral 216 such that an overall current consumed by the system 10 during a boot sequence is less than a current available to charge the system battery 182.

In the context of the example provided above, it should be appreciated that, according to aspects of the embodiments described herein, the application processor 140 may be permitted to start or boot earlier than would be possible otherwise. Specifically, to prevent the system 10 from crashing due to the voltage level VBat drooping below a minimum operating threshold when the application processor 140 is started, one conventional approach has been to wait until the voltage level VBat reaches or exceeds a certain high threshold. Reaching the high threshold may take a relatively significant amount of time when the system battery 182 is being charged depending upon the rate of charge.

When evaluating the system parameters at reference numeral 214, the power processor 132 may consider interplay among operating conditions of the system 10. For example, if the power processor 132 identifies at reference numeral 214 that the voltage level VBat is marginal, then the power processor 132 may also take into consideration the type of battery charger currently coupled to the system bus 180. In other words, the power processor 132 can identify the maximum amount of current available to charge the system battery 182 based on the type of battery charger currently coupled to the system bus 180.

As described above, depending upon the type of charger or port coupled to the system bus 180, the charger or port may be able to source a current of between 100 mA and 1.5 A. If the power processor 132 identifies that the type of battery charger currently coupled to the system bus 180 is one that is able to source only a relatively small amount of current (e.g., 100 mA), then the power processor 132 may recognize that it is possible to boot the application processor 140 at a marginal VBat voltage level—but with a reduced operating frequency. To achieve this faster boot of the application processor 140 with the marginal VBat voltage level, the power processor 132 may set appropriate operating settings in the register bank 150 to start the application processor 140 at the reduced operating frequency. On the other hand, if the type of battery charger is one that is able to source a relatively large amount of current (e.g., 1 A), then the power processor 132 may recognize that it is possible to boot the application processor 140 at a nominal operating frequency even though the voltage level VBat is marginal.

In other aspects, at reference numeral 216, one or more operating parameters may be set for directing the application processor 140 to download a program image source from a host device over the system bus 180. These operating parameters may be set based on a type of charging port (e.g., SDP or CDP port) coupled to the system bus 180, for example, and/or the voltage VBus of the system battery 182. In this case, when the application processor 140 is released for boot, the application processor 140 may identify that an operating parameter for image download is set. The application processor 140 may then proceed to download a program image from the host device via the system bus 180. The download may be based on certain conditions even when the operating parameter for image download is set, such as continued minimum VBat voltage, a temporary halt on charging the system battery 182, etc. The program image may include system software to be installed upon the system 10 during manufacture, for example, and the program image may be stored in the system memory 184. On the other hand, if the system 10 is coupled to a wall charger and not a host device that provides a program image source, the operating parameters may be set to prevent the system 10 from attempting to download the program image source, saving time at the outset of system boot.

It should be appreciated that, in various embodiments, the processes at reference numerals 214 and 216 may occur in combination with each other in an iterative process, as indicated by the dashed line in FIG. 2B.

Continuing, at reference numeral 218, the method 200 includes determining whether to set a power strap option. More particularly, the power processor 132 determines, based on the system parameters, whether to couple one or more of the power rails 120-124 to the voltage level VBus of the system bus 180 using the strap switch 129. At reference numeral 218, the power processor 132 may consider the type of battery charger or charging port coupled to the system bus 180, among other system parameters, when determining whether to set the power strap option. If the power processor 132 determines to rely upon the strap switch 129 to couple VBus, rather than VBat, to one or more of the outputs of the power rails 120-124, then the method 200 proceeds to reference numeral 220. Otherwise, if the power processor 132 determines not to rely upon the strap switch 129, then the method 200 proceeds to reference numeral 222.

As described above, use of the strap switch 129 at reference numeral 218 may permit the system 10 to start or boot faster, because it is not necessary to wait for the system battery 182 to charge to a relatively higher voltage which may be required for operation of certain elements in the system 10, such as the system memory 184 and/or a display of the system 10, for example. Elements in the system 10 that do not require the relatively higher voltage may be powered by power rails supplied by the voltage VBat from the system battery 182. After the voltage VBat of the system battery 182 reaches a voltage sufficient to support the relatively higher voltage, the strap switch 129 may again couple power from the system battery 182 to the power rails for the elements which require the relatively higher voltage.

At reference numeral 220, the method 200 includes setting a strap option for outputs of one or more of the power rails 120-124 using the strap switch 129. The power processor 132 may communicate a command via the serial interface 128 to instruct the PMU 100 to configure the strap switch 129 in a certain way. The strap switch 129, in various embodiments, may be configured by the PMU 100 to couple outputs of one or more of the power rails 120-124 to the voltage level VBus. That is, the power processor 132 may instruct the PMU 100 to couple the power rail for the system memory 184 or the power rail for a display of the system 10, for example, to the voltage level VBus. Such a configuration may be helpful when the system battery 182 is charging, but not enough charge is present in the system battery 182 to support powering one or more of the power rails 120-124 at a sufficient voltage level for operation of the system memory 184 and/or a display of the system 10. It is noted here that, upon setting any strap option, the PMU 100 may update or revise the system parameters stored in the PMU register bank 103 to reflect the status of the strap option. In this manner, the most up-to-date system status parameters are available, and the power processor 132 may re-evaluate the system parameters.

In FIG. 2B, after reference numerals 220 or 218, the method 200 continues to reference numeral 222. At reference numeral 222, the method 200 includes setting power rails for one or more of the application processor 140, the modem 141, the graphics processor 142, or one or more of the subsystems 170-173, for example, among other elements in the system 10. Here, power is supplied to elements of the system 10 which are about to be released to start or boot. The power processor 132 may communicate with the PMU 100 via the serial interface 134 to command the PMU 100 to set the power rails to the appropriate levels based on the evaluating at reference numeral 214 and the strap option settings at reference numeral 220, for example.

At reference numeral 224, the method 200 includes releasing one or more of the application processor 140, the modem 141, the graphics processor 142, or one or more of the subsystems 170-173 for start. For example, at reference numeral 224, the method 200 may include releasing the application processor 140 to start based on an operating parameter stored in the register bank 150. It is noted that, among embodiments, the respective elements of the system 10 may be released for start or boot in any suitable sequence or arrangement. That is, elements of the system 10 may be released respectively in time, in combinations over time, together, etc., depending upon the system parameters and the evaluating at reference numeral 214. Generally, the power processor 132 and/or the PMU 100 may determine which elements of the system 10 should be released for start or boot first, and the process 200 may repeat, in part, for other elements of the system 10.

At reference numeral 226, the method 200 includes starting or booting the elements of the system 10 that were released at reference numeral 224. Here, when the elements of the system 10 start, reference may be made to the operating settings that were stored at reference numeral 204 and/or updated at reference numeral 210 (FIG. 2A). It should be appreciated that, based on the operating settings, when the elements of the system 10 start, the system 10 is able to start with some a priori or beforehand evaluation of the status of the system 10.

Turning to FIG. 3, a process flow diagram is illustrated for a method of evaluation of power and system management information performed by the system 10 of FIG. 1 according to an example embodiment. It is noted that the evaluating by the power processor 132 at reference numeral 214 of FIG. 2B may include any one or more of the evaluating processes illustrated in FIG. 3. Further, it is noted that the processes for evaluation in FIG. 3 may rely upon or correspond to certain processes for measurement performed by the PMU 100 (e.g., at reference numeral 202 of FIG. 2A). That is, the evaluating illustrated in FIG. 3 may depend, at least in part, upon certain system parameters being measured by the PMU 100. Further, in various embodiments, the processes for evaluation in FIG. 3 may be performed by the PMU 100 depending upon the configuration of the system 10.

Among other aspects of the evaluating, the evaluating at reference numeral 214 may include evaluating and/or measuring the battery voltage level VBat of the system battery 182 at reference numeral 302; evaluating and/or detecting a type of battery charger coupled to the system bus 180 and/or the bus voltage level VBus of the system bus 180 at reference numeral 304; evaluating and/or measuring a temperature of a system component of the system 10 at reference numeral 306; and/or, at reference numeral 308, evaluating and/or detecting a feature or option of the system 10, such as whether a program image source is coupled to the system bus 180, whether an external battery charger detection circuit is being relied upon in the system 10, whether an external wireless charging circuit is being relied upon in the system 10, or whether the system 10 is currently under test.

The evaluation processes at one or more of reference numerals 302, 304, 306, or 308 may be performed by the power processor 132 and/or the PMU 100 and include determining whether the battery voltage VBat or the bus voltage VBus is equal to or greater than a predetermined voltage, determining whether a type of battery charger or charging port coupled to the system bus 180 supports at least a predetermined threshold of output current, determining whether a system image is available for download via the system bus 180, determining whether the system 10 is specially configured with optional circuitry or in a test mode, and/or determining whether a temperature of one or more elements of the system 10 are equal to or greater than a predetermined temperature. These evaluations may lead to setting or configuring one or more system operating parameters as described herein, and may be performed in combination with each other at reference numeral 310.

According to aspects of the embodiments described herein, because system parameters of the system 10 are evaluated before elements of the system 10 are released for start, the system 10 is able to start according to a more directed approach. For example, it is not necessary for the application processor 140 to boot, read instructions from the system memory 184, load drivers for communicating with the PMU 100 and/or the system bus 180, communicate with the PMU 100 and/or via the system bus 180, identify the status of the system 10 (e.g., operating voltages, peripherals coupled to the system bus 180, etc.), and make operating decisions according to the status. Instead, according to the more directed approach, the application processor 140 can start with certain operating settings already pre-determined and stored in the register bank 150 (via status flags, status registers, etc.).

It is noted that, if not for the more directed approach, which may include certain limitations on power consumption, for example, the system 10 might otherwise crash because of power failure in certain circumstances. In conventional systems, system boot is typically postponed until an extra buffer of charge is stored in a system battery, to account for high boot-time power demands. Using the more directed approach according to the embodiments described herein, no (or less) charge or voltage buffer is required before boot of the system 10.

The operating settings relied upon during the directed boot may indicate an overall status of the system 10 for reference by the application processor 140. In this context, it should be appreciated that the power processor 132 can make operating decisions for various elements of the system 10 before those elements are released for start. For example, operating parameters such as system temperature may be evaluated and stored for the modem 141 before the modem 141 is released for start. In this manner, the modem 141 may immediately identify and adjust for temperature-dependent communications parameters, for example.

Overall, because the power processor 132 and the PMU 100 are designed to consume relatively low power, the system 10 can benefit from the system parameter measurements and evaluations performed by the power processor 132 and the PMU 100. According to aspects described herein, a more integrated, directed, and flexible approach to start and boot sequences for the elements of the system 10 may be achieved. Generally, the directed and flexible approaches to boot sequences seek to boot the system 10 as quickly as possible, especially in the case of a discharged system battery, while avoiding conditions leading to a system power crash.

In various embodiments, each of the PMU controller 101, the power processor 132, and or other processors or processing circuits of the system 10 may comprise general purpose arithmetic processors, state machines, or Application Specific Integrated Circuits (“ASICs”), for example. Each such processor or processing circuit may be configured to execute one or more computer-readable software instruction modules. In certain embodiments, each processor or processing circuit may comprise a state machine or ASIC, and the processes described in FIGS. 2A, 2B, and 3 may be implemented or executed by the state machine or ASIC according to the computer-readable instructions.

The memories and/or registers described herein may comprise any suitable memory devices that store computer-readable instructions to be executed by processors or processing circuits. These memories and/or registers store computer-readable instructions thereon that, when executed by the processors or processing circuits, direct the processors or processing circuits to execute various aspects of the embodiments described herein.

As a non-limiting example group, the memories and/or registers may include one or more of an optical disc, a magnetic disc, a semiconductor memory (i.e., a semiconductor, floating gate, or similar flash based memory), a magnetic tape memory, a removable memory, combinations thereof, or any other known memory means for storing computer-readable instructions.

In certain aspects, the processors or processing circuits are configured to retrieve computer-readable instructions and/or data stored on the memories and/or registers for execution. The processors or processing circuits are further configured to execute the computer-readable instructions to implement various aspects and features of the embodiments described herein.

Although embodiments have been described herein in detail, the descriptions are by way of example. The features of the embodiments described herein are representative and, in alternative embodiments, certain features and elements may be added or omitted. Additionally, modifications to aspects of the embodiments described herein may be made by those skilled in the art without departing from the spirit and scope of the present invention defined in the following claims, the scope of which are to be accorded the broadest interpretation so as to encompass modifications and equivalent structures. 

At least the following is claimed:
 1. A method, comprising: measuring a system parameter of a system; evaluating the system parameter by a power manager processor; setting an operating parameter for an application processor based on the evaluating; and releasing the application processor to start based on the operating parameter.
 2. The method according to claim 1, further comprising, after setting the operating parameter for the application processor and before releasing the application processor to start, powering a power rail for the application processor.
 3. The method according to claim 1, further comprising: after measuring the system parameter, storing the system parameter in a register bank for evaluation by the power manager processor; powering a power rail for the power manager processor; releasing the power manager processor to start; and upon a request from the power manager processor, communicating the system parameter to the power manager processor.
 4. The method according to claim 1, wherein the operating parameter comprises at least one of an operating frequency or speed, an operating power, or an operating timing for the application processor.
 5. The method according to claim 1, wherein setting the operating parameter comprises setting an operating condition for the application processor to contain an overall current consumption in the system to less than a charging current supplied to a system battery.
 6. The method according to claim 1, wherein measuring the system parameter comprises at least one of: detecting a type of battery charger coupled to a system bus; detecting a program image source coupled to the system bus; measuring a battery voltage of a system battery and a bus voltage of the system bus; measuring a temperature of a system component; or identifying a feature option of the system.
 7. The method according to claim 1, wherein evaluating the system parameter comprises determining whether a battery voltage is equal to or greater than a predetermined voltage.
 8. The method according to claim 1, wherein evaluating the system parameter comprises determining whether a type of battery charger coupled to a system bus supplies at least a predetermined threshold of output current.
 9. The method according to claim 1, further comprising configuring a power strap option based on a battery voltage of a system battery and type of battery charger coupled to a system bus of the system.
 10. The method according to claim 9, wherein configuring the power strap option for the system comprises: based on the type of battery charger, coupling at least one power rail of the system to a bus voltage of the system bus; and setting a boot speed of the application processor based on the battery voltage and the type of battery charger.
 11. A system, comprising: a power management unit that measures a system parameter of a system and stores the system parameter in a memory for evaluation; and a power manager that: evaluates the system parameter; sets an operating parameter for an application processor of the system based on the evaluation; and releases the application processor to start based on the operating parameter.
 12. The system according to claim 11, wherein the operating parameter for the application processor defines a condition of the system that contains an overall current consumption in the system to less than a charging current supplied to a system battery.
 13. The system according to claim 11, wherein the power manager sets, in a register bank, an operating frequency or speed of the application processor based on the evaluation of the system parameter.
 14. The system according to claim 11, wherein the power management unit detects or measures at least one of: a type of battery charger coupled to a system bus; a program image source coupled to the system bus; a battery voltage of a system battery and a bus voltage of the system bus; a temperature of a system component; or a feature option of the system.
 15. The system according to claim 11, wherein the power manager determines whether a battery voltage is equal to or greater than a predetermined voltage and sets an operating parameter for the system based on the determination.
 16. The system according to claim 11, wherein the power manager determines whether a type of battery charger coupled to a system bus supplies at least a predetermined threshold of output current and sets an operating parameter for the application processor based on the determination.
 17. A method, comprising: measuring a system parameter of a system; evaluating the system parameter by a power manager processor; setting an operating parameter for an application processor based on the evaluating; powering a power rail for the power manager processor; and releasing the application processor to start based on the operating parameter.
 18. The method according to claim 17, further comprising: after measuring the system parameter, storing the system parameter in a register bank for evaluation by the power manager processor; powering the power manager processor and releasing the power manager processor to start; and upon a request from the power manager processor, communicating the system parameter to the power manager processor.
 19. The method according to claim 17, wherein setting the operating parameter comprises setting an operating condition for the application processor to contain an overall current consumption in the system to less than a charging current supplied to a system battery.
 20. The method according to claim 17, wherein measuring the system parameter comprises at least one of: detecting a type of battery charger coupled to a system bus; detecting a program image source coupled to the system bus; measuring a battery voltage of a system battery and a bus voltage of the system bus; measuring a temperature of a system component; or identifying a feature option of the system. 